The Imminent Collapse of 1T1C Planar Scaling
For nearly five decades, the Dynamic Random Access Memory (DRAM) industry has relied on the 1T1C (one-transistor, one-capacitor) cell architecture. However, as the industry pushes toward the D1z, D1α, and D1β nodes, the physical limits of scaling the storage capacitor have become a primary bottleneck. In planar DRAM, the capacitor must maintain a capacitance of approximately 25-30 fF to ensure signal integrity and sufficiently long refresh intervals.
As the lateral dimensions shrink, the aspect ratio of these capacitors—currently exceeding 50:1—has reached a point where structural instability and etching depth precision prevent further density gains. To move beyond the 10nm equivalent node, the industry is pivoting toward 3D DRAM, a transition analogous to the shift from 2D to 3D NAND. This shift requires a fundamental change in the channel material, moving away from monocrystalline silicon to Indium Gallium Zinc Oxide (IGZO).
The Physics of IGZO: Why Metal Oxides?
Silicon-based transistors are poorly suited for the back-end-of-line (BEOL) integration required for 3D stacking. High-performance silicon requires high-temperature annealing ($>1000^\circ C$), which would melt the copper interconnects and damage the underlying logic layers. IGZO, a wide-bandgap metal oxide ($E_g \approx 3.1 \text{ eV}$), offers three critical advantages for 3D DRAM:
- Ultra-Low Off-State Leakage ($I_{off}$): Due to its wide bandgap and low intrinsic carrier concentration, IGZO transistors exhibit $I_{off}$ values below $10^{-19}$ A/µm. In contrast, silicon-based DRAM leakage is several orders of magnitude higher.
- BEOL Compatibility: High-quality amorphous or C-Axis Aligned Crystalline (CAAC) IGZO can be deposited via Atomic Layer Deposition (ALD) or physical vapor deposition (PVD) at temperatures below $400^\circ C$.
- High Mobility: While not as fast as bulk silicon, optimized IGZO films achieve field-effect mobility ($\mu_{FE}$) of $30-50 \text{ cm}^2/Vs$, significantly higher than organic or polysilicon alternatives.
"The transition to IGZO represents a shift from material-limited scaling to architecture-limited scaling. By leveraging $I_{off}$ levels that are effectively zero at the femtoampere scale, we can rethink the fundamental DRAM refresh cycle."
2T0C: Eliminating the Capacitor
The move to IGZO enables a radical architecture: the 2T0C (two-transistor, zero-capacitor) cell. By utilizing the extremely low leakage of an IGZO write transistor, the charge can be stored directly on the gate capacitance ($C_g$) of a second read transistor.
The 2T0C Cell Mechanism
- Write Operation: The write transistor (WT) is activated, charging the gate of the read transistor (RT) to a specific voltage level representing a '1' or '0'.
- Storage: Because the IGZO WT has near-zero leakage, the charge on the RT gate remains stable for seconds rather than milliseconds.
- Read Operation: The RT acts as a source follower or a common-source amplifier. The current flowing through the RT bit-line depends on the stored gate charge.
This architecture eliminates the need for the bulky, high-aspect-ratio capacitor, allowing for a significantly thinner cell profile that facilitates vertical stacking of 32, 64, or even 128 tiers of memory.
Fabrication and Integration Challenges
Transitioning IGZO from the lab to a high-volume manufacturing (HVM) environment involves solving complex chemical and structural engineering problems.
1. Oxygen Vacancy Engineering
In IGZO, oxygen vacancies ($V_O$) act as shallow donors. While some vacancies are necessary for conductivity, an excess leads to threshold voltage ($V_{th}$) instability and a shift toward the depletion mode (normally-on). Precise control of the oxygen partial pressure during ALD and subsequent High-Pressure Oxygen Annealing (HPOA) is required to passivate these defects.
2. Hydrogen Passivation
Hydrogen is a ubiquitous contaminant in ALD processes and acts as a potent dopant in IGZO, increasing carrier concentration to the point where the transistor cannot be turned off. Engineers are currently implementing diffusion barriers (such as $Al_2O_3$ or $SiN_x$ layers) to prevent hydrogen migration from the interlayer dielectrics into the IGZO channel.
3. Vertical Channel Transistor (VCT) Geometry
To maximize density, the industry is moving toward Vertical Channel Transistor (VCT) designs. In this configuration, the IGZO channel is deposited on the sidewalls of a high-aspect-ratio pillar or trench.
- Conformal ALD: Achieving a uniform IGZO film thickness of 3-5 nm on vertical sidewalls with a deviation of less than 1% is the current benchmark for yield.
- Gate-All-Around (GAA): VCTs naturally lend themselves to GAA structures, providing superior electrostatic control over the channel and reducing Short Channel Effects (SCE).
Performance Benchmarks: IGZO vs. Polysilicon
Recent data from leading research institutes (IMEC and SEMATECH) comparing 3D-stacked materials highlights why IGZO has become the frontrunner:
| Metric | Polysilicon (3D NAND-like) | CAAC-IGZO (3D DRAM) |
|---|---|---|
| Mobility (cm²/Vs) | 10 - 100 (highly grain dependent) | 30 - 50 (uniform amorphous/crystalline) |
| $I_{off}$ (A/µm) | $10^{-12}$ | $< 10^{-19}$ |
| Subthreshold Swing (mV/dec) | > 100 | 65 - 75 |
| Thermal Budget | > $600^\circ C$ | $< 450^\circ C$ |
| Retention Time | < 10 ms | > 1,000 ms |
The retention time is the standout metric. Standard silicon DRAM requires a refresh every 64ms to 128ms. IGZO-based 2T0C cells have demonstrated retention times exceeding 10 seconds at room temperature, which could reduce DRAM power consumption by 30-50% by nearly eliminating the refresh overhead.
Reliability: PBTI and NBTI
For practicing engineers, the primary concern with metal oxides is Bias Temperature Instability (BTI). Positive Bias Temperature Instability (PBTI) is particularly acute in IGZO. When a positive gate bias is applied, electrons can be trapped at the IGZO/gate-dielectric interface or within the dielectric itself, causing $V_{th}$ to drift.
Research into dual-layer gate dielectrics—combining $HfO_2$ for high capacitance and $Al_2O_3$ for a clean interface—has shown promise in reducing $V_{th}$ shift to less than 50mV over a 10-year projected lifespan at $125^\circ C$.
The Roadmap to 2030
The implementation of IGZO 3D DRAM is expected to follow a three-phase rollout:
- Phase I (2026-2027): Introduction of 1T1C VCT DRAM using IGZO to reduce leakage and allow for initial vertical stacking (up to 8 layers). This maintains the existing capacitor-based bit-line sensing infrastructure.
- Phase II (2028-2029): Transition to 2T0C architectures. This will require a complete redesign of the sense amplifier circuits, as the read mechanism shifts from charge-sharing to current-sensing.
- Phase III (2030+): Logic-on-Memory integration. Because IGZO is BEOL-compatible, DRAM layers will be stacked directly on top of logic wafers (CPU/GPU) without using Through-Silicon Vias (TSVs), enabling "Indium-on-Logic" architectures with bandwidths exceeding 10 TB/s.
Trade-offs and Commercial Viability
Despite the technical advantages, IGZO is not a "drop-in" replacement. The introduction of Indium and Gallium into silicon CMOS lines requires strict cross-contamination protocols. Furthermore, the cost of ALD precursor materials and the increased mask count for vertical stacking will keep 3D DRAM at a price premium initially.
However, the scaling wall for 1T1C is absolute. Without the transition to oxide semiconductors and 3D topologies, the industry faces a stagnation in bit density. As AI models continue to demand exponential increases in local memory capacity, the engineering shift toward IGZO-based 3D DRAM is no longer a research curiosity—it is a manufacturing necessity.