The Transition from Nanosheet to 3D Stacking
As the semiconductor industry pushes beyond the 2nm (N2) node, the traditional scaling of Gate-All-Around (GAA) nanosheet transistors has encountered a fundamental geometric bottleneck. While nanosheets improved electrostatic control over the FinFET, they did not inherently solve the cell-level area limitations imposed by the lateral separation of n-type and p-type transistors. The Complementary FET (CFET) architecture, now entering the pilot line phase for the A14 (1.4nm) and A10 (1nm) generations, addresses this by vertically stacking the n-FET and p-FET devices.
By moving from a side-by-side configuration to a vertical stack, CFET reduces the standard cell track height from 5T or 6T down to 3T or 4T. This transition represents the most significant architectural shift since the introduction of the FinFET in 2011, requiring a total overhaul of Middle-of-Line (MOL) and Back-End-of-Line (BEOL) integration strategies.
Monolithic vs. Sequential CFET Integration
There are two primary pathways for CFET fabrication currently under evaluation by IMEC, TSMC, and Intel: Monolithic and Sequential.
1. Monolithic CFET
In the monolithic approach, both the bottom and top channel layers are grown on the same starting substrate using a single epitaxial process. This involves creating a complex superlattice of alternating Silicon (Si) and Silicon-Germanium (SiGe) layers.
- Advantages: Lower cost due to fewer wafer bonding steps; higher alignment precision between top and bottom gates.
- Challenges: The process requires extremely high-aspect-ratio etching to define the gate trenches through both devices. Selective etching of SiGe sacrificial layers becomes non-linear as depths exceed 200nm, leading to "bowing" in the channel profiles.
2. Sequential CFET
The sequential (or "3D-bonded") approach involves fabricating the bottom FET, then bonding a second thin-film layer on top to fabricate the second FET.
- Advantages: Allows for different channel materials (e.g., Si for n-FET and Germanium (Ge) for p-FET) to optimize carrier mobility independently. It also permits different crystal orientations for each device.
- Challenges: The primary failure mode is the thermal budget. The bonding interface and the bottom device must withstand the high-temperature activation anneals required for the top device without causing dopant diffusion or silicide degradation.
Key Metric: Monolithic CFET can theoretically achieve a 40% reduction in cell area compared to standard GAA nanosheets at the same lithographic pitch, while sequential CFET offers a ~30% gain but with higher performance potential due to heterogeneous channel materials.
The Role of High-NA EUV Lithography
CFET fabrication is inextricably linked to the deployment of High-NA (0.55 NA) EUV lithography. At the 1.4nm node, the metal pitch (MP) shrinks to approximately 18-22nm. Standard 0.33 NA EUV systems require multi-patterning (litho-etch-litho-etch) to resolve these features, which compounds overlay errors and increases defect density.
High-NA EUV allows for single-exposure patterning of the critical active-to-active (AA) and gate (GT) layers. However, the depth of focus (DoF) in High-NA systems is significantly reduced. In a CFET stack, which can be 3-4 times taller than a standard nanosheet, maintaining focus across the entire vertical topography of the gate trench is a major yield detractor. Engineers are compensating for this using advanced photoresist materials and multi-layer hardmasks with high etch selectivity.
Critical Engineering Challenges
High-Aspect-Ratio Etching and Cleaning
The core difficulty in CFET lies in the dual-gate integration. Designers must electrically isolate the top and bottom gates or provide a common gate connection depending on the logic cell type (e.g., an inverter vs. a NAND gate). This requires:
- Selective Gate Recession: Removing part of the gate metal from either the top or bottom device without damaging the high-k dielectric.
- Middle-of-Line (MOL) Congestion: Routing the source/drain (S/D) contacts to the bottom device is significantly hindered by the presence of the top device. This necessitates "tall" via structures that exhibit high parasitic resistance.
Thermal Resistance and Self-Heating
In a CFET structure, the top transistor is thermally isolated from the bulk silicon substrate by the bottom transistor and several layers of interfacial oxides.
- Thermal Resistivity (Rth): Simulation data indicates that CFET devices experience a 20-30% increase in self-heating compared to lateral nanosheets.
- Failure Modes: Elevated temperatures accelerate Bias Temperature Instability (BTI), leading to premature threshold voltage (Vt) shift and decreased device longevity. Heat dissipation strategies now include the use of Backside Power Delivery Networks (BSPDN) to act as a secondary thermal sink.
Backside Power Delivery: The Necessary Companion
CFET is effectively non-viable without Backside Power Delivery Networks (BSPDN), such as Intel’s PowerVia or TSMC’s SuperPower technology. In traditional front-side delivery, power and signal lines compete for the same BEOL metal layers, creating IR drop and congestion.
BSPDN moves the power distribution (Vdd and Vss) to the back of the wafer, utilizing Through-Silicon Vias (TSVs) or Nano-TSVs to connect directly to the CFET source/drain regions.
- IR Drop Reduction: Decoupling power from signal reduces the voltage drop by up to 10-15%, allowing for lower operating voltages (Vdd < 0.6V).
- Routing Efficiency: By removing power rails from the front side, the metal layers can be dedicated entirely to signal routing, which is essential given the 3T track height of CFET cells.
Comparative PPA Analysis
Recent benchmarks comparing N2 GAA to A14 CFET (assuming a monolithic Si-channel implementation) show significant PPA (Power, Performance, Area) shifts:
| Parameter | N2 Nanosheet | A14 CFET | Delta |
|---|---|---|---|
| Standard Cell Height | 5T (90nm) | 3T (54nm) | -40% |
| Effective Drive Current (Ieff) | 1.0x | 1.15x | +15% |
| Parasitic Capacitance (Cgg) | 1.0x | 1.12x | +12% (Higher due to vertical proximity) |
| Power Density | 1.0x | 1.35x | +35% (Requires advanced cooling) |
While CFET offers a massive density boost, the parasitic capacitance between the stacked gates and the S/D regions is a critical trade-off. To mitigate this, researchers are investigating Low-k Spacers using boron-doped carbon-nitrides (SiBCN) to replace standard silicon nitride (SiN) spacers.
Materials Innovation: The Ruthenium Transition
At the CFET scale, the resistivity of copper (Cu) interconnects increases exponentially due to electron surface scattering and the volume occupied by the diffusion barrier (TaN/Ta). To maintain performance, the industry is transitioning to Ruthenium (Ru) for the first several layers of the BEOL and for the MOL contacts.
"Ruthenium is the first viable barrierless metal. Because it does not require a thick liner, the effective cross-sectional area of the wire is maximized, allowing for a 3x reduction in via resistance at the 18nm pitch level."
Ru also exhibits superior electromigration resistance, which is vital because CFET devices, being smaller, will be driven at higher current densities (MA/cm²) to meet performance targets.
Conclusion: The Path to 1nm
The implementation of CFET marks the transition of CMOS technology into a truly three-dimensional era. While the monolithic approach is the current front-runner for the 1.4nm node, the long-term roadmap toward the Sub-1nm (A7/A5) nodes will likely require the sequential approach to integrate high-mobility non-silicon channels like Indium Gallium Zinc Oxide (IGZO) or 2D Transition Metal Dichalcogenides (TMDs).
For the practicing engineer, the move to CFET means that design-technology co-optimization (DTCO) is no longer optional. The interdependence of thermal management, backside power routing, and high-aspect-ratio patterning defines the performance envelope. The 1nm era will not be won by the smallest gate, but by the most efficient vertical integration of the entire stack.