Beyond GAAFET: The Shift to Complementary FET (CFET)

As the industry pushes past the 2nm (N2/A20) nodes, the traditional Gate-All-Around Field-Effect Transistor (GAAFET) architecture—specifically the nanosheet—faces diminishing returns in area scaling. The primary bottleneck is no longer just the gate length ($L_g$), but the contacted poly pitch (CPP) and the track height of the standard cell. To maintain Moore’s Law trajectory toward the A10 (1nm) node, the industry is transitioning to the Complementary FET (CFET).

The fundamental innovation of CFET is the vertical stacking of n-type (nMOS) and p-type (pMOS) devices on top of one another. In current GAA architectures, n-FETs and p-FETs are placed side-by-side, requiring a lateral separation (isolation) that consumes significant die area. By moving to a 3D stacked configuration, the footprint of a standard logic cell can be reduced by nearly 50%, theoretically allowing for a doubling of transistor density without relying solely on lithographic shrinks.

Monolithic vs. Sequential Integration

There are two primary pathways for CFET fabrication currently being vetted by IMEC and major foundries:

1. Monolithic CFET: This involves growing both n- and p-channels on the same starting wafer using a single epitaxial process. It offers the lowest parasitic resistance but requires extremely high-aspect-ratio etching and complex replacement metal gate (RMG) processes to differentiate the work-function metals (WFM) for the top and bottom transistors.
2. Sequential CFET: Also known as 3D integration, this method involves processing the bottom transistor, then bonding a second layer of crystalline silicon (or SiGe) on top for the second transistor. While this simplifies some etching steps, it introduces significant thermal budget constraints; the top layer processing must not exceed ~450°C to avoid damaging the junctions and silicides of the bottom layer.

Solving the Routing Bottleneck: Backside Power Delivery (BSPDN)

As transistors shrink, the metal layers responsible for delivering power (VSS and VDD) and those carrying signals begin to compete for the same narrow routing tracks. In a conventional front-side delivery scheme, the IR drop (voltage drop due to resistance) becomes unsustainable at 1nm dimensions.

Backside Power Delivery Networks (BSPDN) decouple the power delivery from the signal routing. By moving the power rails to the back of the wafer and connecting them directly to the transistor source/drain via Nano-Through-Silicon Vias (nTSVs), engineers can achieve several key performance advantages:

• Total Resistance Reduction: Power delivery resistance is reduced by up to 3x, significantly improving the power integrity of high-performance cores.
• Area Efficiency: Removing power rails from the front-side allows standard cell heights to shrink from 6-track (6T) or 5-track (5T) designs down to 3-track (3T) or even 2.5-track designs.
• Signal Integrity: Reduced congestion on the M0 and M1 metal layers leads to lower crosstalk and simplified routing for the Electronic Design Automation (EDA) tools.

Key Performance Metric: Preliminary benchmarks for A10-class CFETs with BSPDN show a 20% frequency boost at iso-power or a 15-20% area reduction compared to N2-node nanosheet designs.

Materials Engineering: High-Mobility Channels and Ruthenium Interconnects

At the 1nm node, the limitations of copper (Cu) and tungsten (W) become critical. For CFETs, the industry is shifting toward Ruthenium (Ru) for both the buried power rails (BPR) and the lower-level interconnects (M0, M1).

The Case for Ruthenium

Ru offers a lower mean free path for electrons compared to copper, meaning its resistivity increases less dramatically as wire widths shrink below 10nm. Furthermore, Ru does not require the thick diffusion barriers (like TaN) that Cu does, allowing more of the trench volume to be filled with conductive material.

Channel Composition

To achieve balanced drive currents ($I_{on}$) in a stacked configuration, researchers are experimenting with Silicon-Germanium (SiGe) channels for the p-FET to enhance hole mobility, while retaining strained Silicon (Si) for the n-FET. The challenge lies in the epitaxial growth phase, where mismatched lattice constants can introduce dislocations that lead to high leakage currents ($I_{off}$).

Thermal Challenges in 3D Stacked Logic

Thermal management is perhaps the most significant hurdle for CFET adoption. In a standard GAAFET, heat can dissipate through the substrate. In a CFET, the top transistor is thermally isolated from the substrate by the bottom transistor and several layers of dielectric.

Thermal Resistance Benchmarks

Analysis shows that the effective thermal resistance ($R_{th}$) of a stacked CFET can be 1.4x to 1.8x higher than a planar nanosheet. This leads to "self-heating" effects where the junction temperature can rise by 20-30°C above ambient, negatively impacting carrier mobility and long-term reliability (specifically Bias Temperature Instability or BTI).

Engineers are mitigating this through:

• Inner Spacer Engineering: Utilizing high-thermal-conductivity dielectrics (like AlN) for the spacers between the gate and source/drain.
• BSPDN as a Heat Sink: Using the backside metal layers and nTSVs as secondary thermal dissipation paths to pull heat away from the bottom transistor.

Lithography: High-NA EUV Integration

Fabricating CFETs at the 1nm node is impossible without High-NA (0.55 NA) Extreme Ultraviolet (EUV) lithography. The higher numerical aperture provides the resolution necessary to pattern the 16nm to 20nm CPP required for these architectures in a single exposure.

1. Anamorphic Imaging: High-NA scanners use different magnifications in the X and Y directions (4x and 8x). This requires a complete redesign of the mask layout and affects the maximum reticle size (field size), often halving it compared to standard EUV.
2. Stitching Challenges: Because the field size is smaller, many large-die chips (like AI accelerators) require "stitching" two exposures together with sub-nanometer overlay accuracy. Any misalignment leads to parasitic capacitance spikes or outright shorts at the stitch boundary.

Fabrication Flow: The Atomic Layer Etch (ALE) Requirement

The vertical nature of CFET requires unprecedented control over etch profiles. To form the common gate for the stacked n/p pair, the etch must penetrate through multiple layers of Si and SiGe with verticality exceeding 89.5 degrees.

Process Sequence for Monolithic CFET:

1. Multi-layer Epi: Growth of alternating $Si / SiGe$ superlattice (typically 6-8 layers).
2. High-Aspect-Ratio Fin Etch: Defining the active area for both top and bottom devices.
3. Inner Spacer Formation: Highly selective lateral etching of SiGe to create cavities for the gate dielectric.
4. Source/Drain Epitaxy: Bottom p-S/D growth, followed by an isolation oxide layer, then top n-S/D growth.
5. Dual Work Function Metal (WFM) Gate: The most complex step, requiring the deposition of p-WFM, followed by a selective removal from the top device, then deposition of n-WFM.

Trade-offs and Implementation Risks

While CFET offers a clear path to density scaling, the trade-offs are non-trivial:

• Cost: The transition to High-NA EUV and the addition of 30-40% more mask layers significantly increases wafer cost. The cost-per-transistor parity may not be reached until high-volume manufacturing (HVM) matures in 2027.
• Yield: The complexity of the n/p isolation layer—a thin dielectric layer between the two transistors—is a major yield killer. Any pinhole in this layer results in a VDD-to-VSS short.
• Design Complexity: Standard cell libraries must be entirely rewritten. The move to 3T tracks leaves very little room for "fix-up" cells or decoupling capacitors within the logic blocks.

Summary of A10 Node Specifications

Parameter	Value (Target)
Contacted Poly Pitch (CPP)	42 - 45 nm
Metal Pitch (MP)	16 - 18 nm
Standard Cell Height	< 120 nm (3T)
Gate Length ($L_g$)	10 - 12 nm
Drive Current Improvement	+15% vs N2
Leakage ($I_{off}$)	< 100 nA/um

Conclusion

The move to CFET at the 1nm node represents the most significant architectural shift in the history of the semiconductor industry, surpassing the transition from FinFET to GAA. By leveraging vertical stacking and backside power delivery, foundries can circumvent the physical limits of 2D scaling. However, the success of this transition hinges on mastering the thermal management and overlay precision required by the 3D logic era. For researchers, the focus now shifts from simple scaling to the materials science of 3D heat dissipation and the reliability of ultra-thin isolation dielectrics.